A Comparative Study of Low Power Testing Techniques for Digital Circuits

Suhas B Shirol, Rajashekar B Shettar

Abstract


In recent years, with fast growth of mobile communication and portable computing systems, design for low power has become the challenge in the field of Digital VLSI design. The main focus of the paper is to make a comparative study of low power Linear Feedback Shift Register (LFSR) architecture such as Built In Self Test (BIST), it has been often seen that during test mode process the power consumed is  much higher, when compared to that of normal mode process test as there is high switching activity in the nodes of Circuit Under Test(CUT) during testing.

Full Text:

PDF

References


Sunghoon Chun, Taejin Kim and Sungho Kang, "A New Low Energy BIST Using A Statistical Code," IEEE, pp. 647-652, 2008

Lubna Naim and Tarana A. Chandel, “Design of Low Transition Pseudo-Random Pattern Generator for BIST Applications,” International Journal of Computer Applications., vol. 87, no. 15, February 2014.

Abu-Issa and S. Quigley, Bit-swapping LFSR and scan-chain ordering: A novel technique for peak- and average-power reduction in scan-based BIST, IEEE Trans. Compute.- Aided Design Integral. Circuits Syst., vol. 28, no. 5, pp. 755–759, May 2009.

Mehrdad Nourani, Mohammad Tehranipoor and Nisar Ahmed, “Low-Transition Test Pattern Generation for BIST-Based Applications,” IEEE Transactions on Computers., vol. 57, no. 3, pp. 303-315, March 2008.

Praveen J, and M N Shanmukhaswamy, “Power Reduction Technique in LFSR using Modified Control Logic for VLSI Circuit,” International Conference on Electronic Design and Signal Processing (ICEDSP) 2012.

V. Agrawal, C.R. Kime, and K. Saluja, "A tutorial on built-in self-test - part 1: principles", IEEE Design and Test of Computers, pp. 73-82, March 1993.

V. Agrawal, C.R. Kime, and K.K. Saluja, "A tutorial on built-in self test - part 2: applications", IEEE Design and Test of Computers, pp. 69-77, June 1993.

V. Agrawal, C.-J. Lin, P.W. Rutkowski, S. Wu, and Y. Zorian, "Built-in self-test for digital integrated circuits", AT&T Technical Journal, pp. 30-39, March 1994.

P.H. Bardell, W.H. McAnney, and J. Savir, Built-in test for VLSI: pseudorandom techniques, John Wiley & Sons, 1987.

Mehdi Salmani Jelodar, Kiarash Mizanian, " Power Aware Scan-based Testing using Genetic Algorithm," IEEE CCECE/CCGEI, Ottawa, May 2006

S. Chakravarty and V. Dabholkar, “Minimizing Power Dissipation in Scan Circuits During Test Application”, IEEE International Workshop on Low Power Design, 1994, pp. 51-56.

P. Girard, C. Landrault, S. Pravossoudovitch and D. Severac, “Reducing Power Consumption during Test Application by Test Vector Ordering,” IEEE Intl. Symposium on Circuits and Systems, 1998, pp. 296-299.

P. Raja Gopal , S. Saravanan, " Low Power Estimation on Test Compression Technique for SoC based Design, " Indian Journal of Science and Technology, Vol 8(14), July2015

M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1990.

N.-C. Lai and S.-Y. Wang, "Low-capture-power test generation by specifying a minimum set of controlling inputs", Asian Test Symposium, pp. 413-418, October 2007.

P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, and M. Santos, "Low energy BIST design: Impact of the LFSR TPG parameters on the weighted switching activity", Proceedings of International Symposium on Circuits and Systems, pp. 110-113, June 1999.

M. Brazzarola and F. Fummi, "Power characterization of LFSRs", International Survey on Defect and Fault Tolerance in VLSI Systems, pp139-147, November 1999.

B. Ayari and B. Kaminska, “A New Dynamic Test Vector Compaction for Automatic Test Pattern Generation”, IEEE, Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 3, March 1994.

Giri, C., Choudhary P.K. , Chattopadhyay S., "Scan Architecture Modification with Test Vector Reordering for Test Power Reduction ," International Symposium on Integrated Circuits, ISIC '07, 2007

R. Sankaralingam and N. Touba, "Multi-phase shifting to reducing instantaneous peak power during scan", Proceedings of Latin American Workshop, pp. 78-83, February 2003.

L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, San Francisco, Morgan Kaufmann, 2006.

Chandra and K. Chakrabarty, "Combining low-power scan testing and test data compression for system on-a-chip", Proceedings of Design Automation Conference, pp. 166-169, June 2001.

Chandra and K. Chakrabarty, "Reduction of SOC test data volume, scan power and testing time using alternating run-length codes", Proceedings of Design Automation Conference, pp. 673-678, June 2002.

P. Rosinger, B.M. Al-Hashimi, and N. Nicolici, "Low power mixed-mode BIST based on mask pattern generation using dual LFSR- reseeding", Proceedings of International Conference on Computer Design, pp. 474-479, 2002.

J. Lee and N. Touba, "Low power test data compression based on LFSR reseeding", Proceedings of International Conference on Computer Design, pp. 180-185, October 2004.

Chandan Giri, P.K. Choudhary and Santanu Chattopadhyay "Scan Power Reduction Through Scan Architecture Modification And Test Vector Reordering, " ASIAN TEST SYMPOSIUM , NOVEMBER 2007.S. M. Metev and V. P. Veiko, Laser Assisted Microtechnology, 2nd ed., R. M. Osgood, Jr., Ed. Berlin, Germany: Springer-Verlag, 1998.




DOI: https://doi.org/10.23956/ijarcsse/V7I7/0180

Refbacks

  • There are currently no refbacks.


Bookmark and Share


© International Journals of Advanced Research in Computer Science and Software Engineering (IJARCSSE)| All Rights Reserved | Powered by Advance Academic Publisher.