Modelling, Designing and Analysis of Phase Locked Loop Using Pyxis Tool of Mentor Graphics

Rasika M. Chandramore, S. A. Patil

Abstract


This paper introduces a design aspects of low power phase locked loop using VLSI technology.The phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main quality related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described.

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References


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DOI: https://doi.org/10.23956/ijarcsse/V7I6/0172

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